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4-mbit (256k x 16) static ram cy7c1041cv33 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-05134 rev. *e revised july 19, 2004 features ? pin equivalent to cy7c1041bv33 ? temperature ranges ? commercial: 0c to 70c ? industrial: ?40c to 85c ? automotive: ?40c to 125c ?high speed ?t aa = 10 ns ? low active power ? 324 mw (max.) ? 2.0v data retention ? automatic power-down when deselected ? ttl-compatible inputs and outputs ? easy memory expansion with ce and oe features functional description [1] the cy7c1041cv33 is a high-performance cmos static ram organized as 262,144 words by 16 bits. writing to the device is accomplished by taking chip enable (ce ) and write enable (we ) inputs low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 ?i/o 7 ), is written into the location specified on the address pins (a 0 ?a 17 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 ?i/o 15 ) is written into the location specified on the address pins (a 0 ?a 17 ). reading from the device is accomplished by taking chip enable (ce ) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 0 ? i/o 7 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . see the truth table at the back of this data sheet for a complete description of read and write modes. the input/output pins (i/o 0 ?i/o 15 ) are placed in a high-impedance state when the device is deselected (ce high), the outputs are disabled (oe high), the bhe and ble are disabled (bhe , ble high), or during a write operation (ce low, and we low). the cy7c1041cv33 is available in a standard 44-pin 400-mil-wide body width soj and 44-pin tsop ii package with center power and ground (revolutionary) pinout, as well as a 48-ball fine-pitch ball grid array (fbga) package. notes: 1. for guidelines on sram system design, please refer to the ?syst em design guidelines? cypress application note, available on t he internet at www.cypress.com . 14 15 logic block diagram pin configuration a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer 256k 16 array a 0 a 11 a 13 a 12 a a a 16 a 17 a 9 a 10 1024 x 4096 i/o 0 ?i/o 7 oe i/o 8 ?i/o 15 ce we ble bhe top view soj tsop ii we 1 2 3 4 5 6 7 8 9 10 11 14 31 32 36 35 34 33 37 40 39 38 12 13 41 44 43 42 16 15 29 30 v cc a 5 a 6 a 7 a 8 a 0 a 1 oe v ss a 17 i/o 15 a 2 ce i/o 2 i/o 0 i/o 1 bhe a 3 a 4 18 17 20 19 i/o 3 27 28 25 26 22 21 23 24 v ss i/o 6 i/o 4 i/o 5 i/o 7 a 16 a 15 ble v cc i/o 14 i/o 13 i/o 12 i/o 11 i/o 10 i/o 9 i/o 8 a 14 a 13 a 12 a 11 a 9 a 10 nc
cy7c1041cv33 document #: 38-05134 rev. *e page 2 of 12 selection guide -8 -10 -12 -15 -20 unit maximum access time 8 10121520ns maximum operating current commercial 10090858075ma industrial 110 100 95 90 85 ma automotive ----90ma maximum cmos standby current commercial/ industrial 10 10 10 10 10 ma automotive ----15ma shaded areas contain advance information. pin configurations 48-ball mini fbga (top view) we v cc a 11 a 10 nc a 6 a 0 a 3 ce i/o 2 i/o 0 i/o 1 a 4 a 5 i/o 3 i/o 5 i/o 4 i/o 6 i/o 7 v ss a 9 a 8 oe v ss a 7 i/o 8 bhe nc a 17 a 2 a 1 ble v cc i/o 9 i/o 10 i/o 11 i/o 12 i/o 13 i/o 14 i/o 15 a 15 a 14 a 13 a 12 nc nc nc 3 2 6 5 4 1 d e b a c f g h a 16
cy7c1041cv33 document #: 38-05134 rev. *e page 3 of 12 pin definitions pin name 44-soj, 44-tsop pin number 48-ball fbga pin number i/o type description a 0 -a 17 1-5,18-27, 42-44 a3,a4,a5,b3, b4,c3,c4,d4, h2,h3,h4,h5,g 3,g4,f3,f4,e4, d3 input address inputs used to select one of the address locations. i/o 0 - i/o 15 7-10,13-16, 29-32,35-38 b1,c1,c2,d2,e 2,f2,f1,g1,b6, c6,c5,d5,e5, f5,f6,g6 input/output bidirectional data i/o lines. used as input or output lines depending on operation nc [2] 28 a6,e3,g2,h1, h6 no connect no connects. this pin is not connected to the die we 17 g5 input/control write enable input, active low. when selected low, a write is conducted. when selected high, a read is conducted. ce 6 b5 input/control chip enable input, active low. when low, selects the chip. when high, deselects the chip. bhe , ble 39,40 a1,b2 input/control byte write select inputs, active low. bhe controls i/o 7 -i/o 0 , ble controls i/o 15 -i/o 8 . oe2 41 a2 input/control output enable, active low. controls the direction of the i/o pins. when low, the i/o pins are allowed to behave as outputs. when deasserted high, i/o pins are three-stated, and act as input data pins. v ss 12,34 d1,e6 ground ground for the device. should be connected to ground of the system. v cc 11,33 d6,e1 power supply power supply inputs to the device. notes: 2. nc pins are not connected on the die.
cy7c1041cv33 document #: 38-05134 rev. *e page 4 of 12 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ?65 c to +150 c ambient temperature with power applied............................................. ?55 c to +125 c supply voltage on v cc to relative gnd [3] .... ?0.5v to +4.6v dc voltage applied to outputs in high-z state [3] ....................................?0.5v to v cc + 0.5v dc input voltage [3] .................................?0.5v to v cc + 0.5v current into outputs (low).... ..................................... 20 ma operating range range ambient temperature v cc commercial 0 c to +70 c3.3v 0.3v industrial ?40 c to +85 c automotive ?40 c to +125 c dc electrical characteristics over the operating range parameter description test conditions -8 -10 -12 -15 -20 uni t min. max. min. max. min. max. min. max. min. max. v oh output high voltage v cc = min., i oh = ?4.0 ma 2.4 2.4 2.4 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 0.4 0.4 0.4 v v ih input high voltage 2.0 v cc + 0.3 2.0 v cc + 0.3 2.0 v cc + 0.3 2.0 v cc + 0.3 2.0 v cc + 0.3 v v il [3] input low voltage ?0.3 0.8 ?0.3 0.8 ?0.3 0.8 ?0.3 0.8 ?0.3 0.8 v i ix input load current gnd < v i < v cc com?l / ind?l ?1 +1 ?1 +1 ?1 +1 ?1 +1 ?1 +1 a automotive - -------?20+20 a i oz output leakage current gnd < v out < v cc , output disabled com?l / ind?l ?1 +1 ?1 +1 ?1 +1 ?1 +1 ?1 +1 a automotive - -------?20+20 a i cc v cc operating supply current v cc = max., f = f max = 1/t rc comm?l 100 90 85 80 75 ma ind?l 110 100 95 90 85 ma automotive -- - -90ma i sb1 automatic ce power-down current ?ttl inputs max. v cc , ce > v ih v in > v ih or v in < v il , f = f max com?l / ind?l 40 40 40 40 40 ma automotive -- - -45ma i sb2 automatic ce power-down current ?cmos inputs max. v cc , ce > v cc ? 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 com?l / ind?l 10 10 10 10 10 ma automotive -- - -15ma shaded areas contain advance information. capacitance [4] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 8 pf c out i/o capacitance 8 pf thermal resistance [4] parameter description test conditions 44-pin tsop-ii (non pb-free) 48-fbga (non pb-free) unit ja thermal resistance (junction to ambient) test conditions fo llow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. 76.85 92.78 c/w jc thermal resistance (junction to case) 11.26 8.88 c/w notes: 3. v il (min.) = ?2.0v and v ih (max) = v cc + 0.5v for pulse durations of less than 20 ns. 4. tested initially and after any design or process changes that may affect these parameters.
cy7c1041cv33 document #: 38-05134 rev. *e page 5 of 12 ac switching characteristics [5] over the operating range parameter description -8 -10 -12 -15 -20 unit min. max. min. max. min. max. min. max. min. max. read cycle t power [6] v cc (typical) to the first access 1 11 1 1 s t rc read cycle time 8 10 12 15 20 ns t aa address to data valid 810121520ns t oha data hold from address change 3 33 3 3ns t ace ce low to data valid 810121520ns t doe oe low to data valid 45 6 7 8ns t lzoe oe low to low-z 0 00 0 0ns t hzoe oe high to high-z [7, 8] 45 6 7 8ns t lzce ce low to low-z [8] 3 33 3 3ns t hzce ce high to high-z [7, 8] 45 6 7 8ns t pu ce low to power-up 0 00 0 0ns t pd ce high to power-down 810121520ns t dbe byte enable to data valid 45 6 7 8ns t lzbe byte enable to low-z 0 00 0 0ns t hzbe byte disable to high-z 66 6 7 8ns write cycle [9, 10] t wc write cycle time 8 10 12 15 20 ns t sce ce low to write end 6 7 8 10 10 ns t aw address set-up to write end 6 7 8 10 10 ns t ha address hold from write end 0 00 0 0ns t sa address set-up to write start 0 00 0 0ns t pwe we pulse width 6 7 8 10 10 ns t sd data set-up to write end 4 56 7 8ns t hd data hold from write end 0 00 0 0ns t lzwe we high to low-z [8] 3 33 3 3ns t hzwe we low to high-z [7, 8] 45 6 7 8ns t bw byte enable to end of write 6 7 8 10 10 ns shaded areas contain advance information. notes: 5. test conditions assume signal transition ti me of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3. 0v. 6. t power gives the minimum amount of time that the power supply should be at typical v cc values until the first memory access can be performed. 7. t hzoe , t hzce , and t hzwe are specified with a load capacitance of 5 pf as in part (d) of ac test loads. transition is measured 500 mv from steady-state voltage. 8. at any given temperature and voltage condition, t hzce is less than t lzce , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. 9. the internal write time of the memo ry is defined by the overlap of ce low, and we low. ce and we must be low to initiate a write, and the transition of either of these signals can terminate the write. the input dat a set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 10. the minimum write cycle time for write cycle no. 3 (we controlled, oe low) is the sum of t hzwe and t sd .
cy7c1041cv33 document #: 38-05134 rev. *e page 6 of 12 ac test loads and waveforms [11] switching waveforms notes: 11. ac characteristics (except high-z) for all 8-ns and 10-ns part s are tested using the load conditions shown in figure (a). al l other speeds are tested using the thevenin load shown in figure (b). high-z characteristics are test ed for all speeds using the test load shown in figure (d). 12. device is continuously selected. oe , ce , bhe and/or bhe = v il . 13. we is high for read cycle. 14. address valid prior to or coincident with ce transition low. 90% 10% 3.0v gnd 90% 10% all input pulses 3.3v output 30 pf * capacitive load consists of all components of the test environment (b) r 317 ? r2 351 ? rise time: 1 v/ns fall time: 1 v/ns 30 pf* output z = 50 ? 50 ? 1.5v (c) (a) 3.3v output 5 pf (d) r 317 ? r2 351 ? 8-, 10-ns devices 12-, 15-, 20-ns devices high-z characteristics read cycle no. 1 previous data valid data valid t rc t aa t oha address data out [12, 13] read cycle no. 2 (oe controlled) 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd high oe ce icc isb impedance address data out v cc supply t dbe t lzbe t hzce bhe , ble [13, 14] current i cc i sb
cy7c1041cv33 document #: 38-05134 rev. *e page 7 of 12 notes: 15. data i/o is high-impedance if oe or bhe and/or ble = v ih . 16. if ce goes high simultaneously with we going high, the output remains in a high-impedance state. switching waveforms (continued) write cycle no. 1 (ce controlled) t hd t sd t sce t sa t ha t aw t pwe t wc bw datai/o address ce we bhe, ble [15, 16] t write cycle no. 2 (ble or bhe controlled) t hd t sd t bw t sa t ha t aw t pwe t wc t sce datai/o address bhe ,ble we ce
cy7c1041cv33 document #: 38-05134 rev. *e page 8 of 12 truth table ce oe we ble bhe i/o 0 ?i/o 7 i/o 8 ?i/o 15 mode power h x x x x high-z high-z power-down standby (i sb ) l l h l l data out data out read all bits active (i cc ) l l h l h data out high-z read lower bits only active (i cc ) l l h h l high-z data out read upper bits only active (i cc ) l x l l l data in data in write all bits active (i cc ) l x l l h data in high-z write lower bits only active (i cc ) l x l h l high-z data in write upper bits only active (i cc ) l h h x x high-z high-z selected, outputs disabled active (i cc ) switching waveforms (continued) write cycle no. 3 (we controlled, oe low) t hd t sd t sce t ha t aw t pwe t wc t bw data i/o address ce we bhe , ble t sa t lzwe t hzwe
cy7c1041cv33 document #: 38-05134 rev. *e page 9 of 12 ordering information cy7c1041cv33 speed (ns) ordering code package name package type operating range 10 cy7c1041cv33-10bac ba48b 48-ball fine pitch bga commercial cy7c1041cv33-10vc v34 44-lead (400-mil) molded soj cy7c1041cv33-10zc z44 44-pin tsop ii z44 cy7c1041cv33-10zxc z44 lead (pb)-free, 44-pin tsop ii z44 cy7c1041cv33-10bai ba48b 48-ball fine pitch bga industrial cy7c1041cv33-10vi v34 44-lead (400-mil) molded soj cy7c1041cv33-10zi z44 44-pin tsop ii z44 cy7c1041cv33-10zxi z44 lead (pb)-free, 44-pin tsop ii z44 12 cy7c1041cv33-12bac ba48b 48-ball fine pitch bga commercial cy7c1041cv33-12vc v34 44-lead (400-mil) molded soj cy7c1041cv33-12zc z44 44-pin tsop ii z44 cy7c1041cv33-12zxc z44 lead (pb)-free, 44-pin tsop ii z44 cy7c1041cv33-12bai ba48b 48-ball fine pitch bga industrial cy7c1041cv33-12vi v34 44-lead (400-mil) molded soj cy7c1041cv33-12zi z44 44-pin tsop ii z44 cy7c1041cv33-12zxi z44 lead (pb)-free, 44-pin tsop ii z44 15 cy7c1041cv33-15bac ba48b 48-ball fine pitch bga commercial cy7c1041cv33-15vc v34 44-lead (400-mil) molded soj cy7c1041cv33-15zc z44 44-pin tsop ii z44 cy7c1041cv33-15zxc z44 lead (pb)-free, 44-pin tsop ii z44 cy7c1041cv33-15bai ba48b 48-ball fine pitch bga industrial cy7c1041cv33-15vi v34 44-lead (400-mil) molded soj cy7c1041cv33-15zi z44 44-pin tsop ii z44 cy7c1041cv33-15zxi z44 lead (pb)-free, 44-pin tsop ii z44 20 cy7c1041cv33-20bac ba48b 48-ball fine pitch bga commercial CY7C1041CV33-20VC v34 44-lead (400-mil) molded soj cy7c1041cv33-20zc z44 44-pin tsop ii z44 cy7c1041cv33-20bai ba48b 48-ball fine pitch bga industrial cy7c1041cv33-20vi v34 44-lead (400-mil) molded soj cy7c1041cv33-20zi z44 44-pin tsop ii z44 cy7c1041cv33-20bae ba48b 48-ball fine pitch bga automotive cy7c1041cv33-20ve v34 44-lead (400-mil) molded soj cy7c1041cv33-20ze z44 44-pin tsop ii z44
cy7c1041cv33 document #: 38-05134 rev. *e page 10 of 12 package diagrams 48-ball (7.00 mm x 8.5 mm x 1.2 mm) fbga ba48b 51-85106-*d 44-lead (400-mil) molded soj v34 51-85082-*b
cy7c1041cv33 document #: 38-05134 rev. *e page 11 of 12 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. all products and company names mentioned in this docum ent may be the trademarks of their respective holders. package diagrams (continued) 44-pin tsop ii z44 51-85087-*a
cy7c1041cv33 document #: 38-05134 rev. *e page 12 of 12 document history page document title: cy7c1041cv33 4-mbit (256k x 16) static ram document number: 38-05134 rev. ecn no. issue date orig. of change description of change ** 109513 12/13/01 hgk new data sheet *a 112440 12/20/01 bss updated 51-85106 from revision *a to *c *b 112859 03/25/02 dfp added cy7c1042cv33 in bga package removed 1042 bga option pin acc final data sheet *c 116477 09/16/02 cea add applications foot note to data sheet *d 119797 10/21/02 dfp added 20-ns speed bin *e 262949 see ecn rkf 1) added lead (pb)-free parts in the ordering info (page #9) 2) added automotive specs to datasheet

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